Generally, a random access memory can be classified into a static random access memory (SRAM) and a dynamic random access memory (DRAM). When a SRAM is powered, the data stored in the SRAM will not be lost. Unlike the SRAM, the data stored in the DRAM needs to be periodically refreshed, otherwise the data will be lost. Since the SRAM has a symmetrical configuration, the data accessing speed of each SRAM cell is faster than that of each DRAM cell at the same operating frequency. Although SRAM is more costly than DRAM, the cache memory of the personal computer is usually implemented by SRAM. A conventional SRAM cell consists of six transistors. Such SRAM cell is also referred as a six-transistor static random access memory (6T SRAM).
Referring to FIG. 1, a schematic circuit diagram of a conventional 6T SRAM cell is illustrated. The 6T SRAM cell comprises a flip-flop and two access transistors. The flip-flop includes a pair of cross-coupling inverters. The first inverter includes a first transistor Q1 and a third transistor Q3. The source electrode of the third transistor Q3 is connected to a power source voltage Vcc. The drain electrode of the third transistor Q3 is connected to the output terminal of the first inverter. The gate electrode of the third transistor Q3 is connected to the input terminal of the first inverter. The source electrode of the first transistor Q1 is connected to a ground terminal. The drain electrode of the first transistor Q1 is connected to the output terminal of the first inverter. The gate electrode of the first transistor Q1 is connected to the input terminal of the first inverter. The second inverter includes a second transistor Q2 and a fourth transistor Q4. The source electrode of the fourth transistor Q4 is connected to the power source voltage Vcc. The drain electrode of the fourth transistor Q4 is connected to the output terminal of the second inverter. The gate electrode of the fourth transistor Q4 is connected to the input terminal of the second inverter. The source electrode of the second transistor Q2 is connected to the ground terminal. The drain electrode of the second transistor Q2 is connected to the output terminal of the second inverter. The gate electrode of the second transistor Q2 is connected to the input terminal of the second inverter. The input terminal of the first inverter is connected with the output terminal of the second inverter. The input terminal of the second inverter is connected with the output terminal of the first inverter.
The first access transistor Q5 is interconnected between the output terminal of the first inverter and a bit line BL. The second access transistor Q6 is interconnected between the output terminal of the second inverter and an inverted bit line (/BL). The gate electrodes of the first access transistor Q5 and the second access transistor Q6 are connected to the word line WL. According to the voltage level of the word line signal, the first access transistor Q5 and the second access transistor Q6 are selectively turned on or turned off. That is, the first access transistor Q5 and the second access transistor Q6 are switch elements controllable by the word line signal. The first access transistor Q5 and the second access transistor Q6 are also referred as the pass-gate transistors.
Furthermore, the bit line BL and the inverted bit line (/BL) are both connected to a sense amplifier (not shown). When the first access transistor Q5 and the second access transistor Q6 are turned on in response to the word line signal, the signals of the bit line BL and the inverted bit line (/BL) are outputted from the SRAM through the sense amplifier (not shown).
FIG. 2 is a schematic circuit block diagram of a conventional SRAM. As shown in FIG. 2, the SRAM 100 comprises a main control circuit 10, a column decoder 20, a row decoder 30, a memory cell array 40, and a sense amplifier and input/output control circuit 50. The main control circuit 10 can receive multiple address signals ADD, a clock signal CLK and a read/write signal R/W. The address signals ADD include column address signals and row address signals. The column address signals are transmitted to the column decoder 20 for controlling the bit lines. The row address signals are transmitted to the row decoder 30 for controlling the word lines. The sense amplifier and input/output control circuit 50 is connected to the bit lines. For writing data into the SRAM 100, the input data signals are written into specified memory cells through the sense amplifier and input/output control circuit 50. For reading from the SRAM 100, the data stored in specified memory cells are outputted as the output data signals through the sense amplifier and input/output control circuit 50.
As known, the 6T SRAM cell occupies a large layout area. For increasing the area utilization, the number of transistors contained in the SRAM cell needs to be reduced. Recently, 1T SRAM cell and 2T SRAM cell have been disclosed. Since the 6T SRAM cell has a latch, it is not necessary to refresh the 6T SRAM cell. Due to a leakage current, the data stored in the 1T or 2T SRAM cell are possibly lost. For preventing from data loss, the SRAM 100 has an additional hidden refresh unit and the timing of performing the data refresh operation is properly decided. As such, the user does not need an external data refreshing circuit to perform the data refresh operation of the SRAM.
FIG. 3 is a schematic circuit block diagram of another conventional SRAM. As shown in FIG. 3, the SRAM 100 comprises a main control circuit 10, a column decoder 20, a row decoder 30, a memory cell array 40, a sense amplifier and input/output control circuit 50, and a hidden refresh unit 60. The hidden refresh unit 60 is connected to the main control circuit 10 and the row decoder 30. In comparison with FIG. 2, the main control circuit 10 of the SRAM 100 of FIG. 3 generates address signals to the row decoder 30 during the idle accessing cycle according to the action of the hidden refresh unit 60, thereby refreshing the memory cell array 40. The memory cells of the memory cell array 40 are 1T or 2T SRAM cells. Furthermore, if no clock signal CLK is received by the main control circuit 10, the main control circuit 10 can refresh data of the memory cell array 40 according to the clock signal and the address signals that are generated by the hidden refresh unit 60 and transmitted to the row decoder 30. In other words, by means of the hidden refresh unit 60, the layout area of the SRAM is reduced.
For example, MOSYS Corporation has proposed a 1T SRAM cell. The 1T SRAM cell does not posses two bit lines. Since the sense amplifier is based on a single-ended sensing scheme and includes positive and negative charge pumps, a high standby current occurs. Moreover, the 1T SRAM cell needs an additional refresh control mechanism. Importantly, since the 1T SRAM cell is not compatible with the word line and the bit line of the 6T SRAM cell, the 1T SRAM cell fails to replace the 6T SRAM cell to be used in the application-specific integrated circuit (ASIC).
In addition, XMEM Corporation has proposed a 2T SRAM cell. The 2T SRAM cell is consisted of two PMOS transistors. Since the sense amplifier of the 2T SRAM cell also includes positive and negative charge pumps, the standby current is high. That is, the 2T SRAM cell is not feasible to be used in the application-specific integrated circuit (ASIC).
FIG. 4 is a schematic circuit diagram illustrating another conventional SRAM cell. The SRAM cell is disclosed in US Patent Application No. 20050226079, entitled “Method and apparatus for dual port memory devices having hidden refresh and double bandwidth”. As shown in FIG. 4, the SRAM cell comprises two switches 201, 202 and a storage node 211. The storage node 211 is consisted of a PMOS transistor. The storage node 211 can be referred as a PMOS capacitor. The gate electrode of the PMOS transistor is connected to an external voltage VCAPEN. The switches 201 and 202 are also PMOS capacitors. The storage node 211 is interconnected between first terminals of these two switches 201 and 202. The second terminal of the switch 201 is connected to a read and refresh bit line (BLRRF). The control terminal of the switch 201 is connected to a read and refresh word line. The second terminal of the switch 202 is connected to a write bit line (BLW). The gate terminal of the switch 202 is connected to a write word line.
Since the SRAM cell comprises two switches 201, 202 and a storage node 211, the SRAM cell is also referred as a 2T1C SRAM cell. The sense amplifier of the 2T1C SRAM cell is also based on a single-ended sensing scheme. In addition, the word line and the bit line of the 2T1C SRAM cell fail to be compatible with the word line and the bit line of other conventional SRAM cell.